1. Field of the Invention
The present invention relates generally to a data reading method for use in a semiconductor memory device and a semiconductor memory device capable of executing the method. More particularly, this invention relates to a method of shortening the time necessary for a semiconductor memory device to perform data reading operations immediately following data writing operations.
2. Description of the Related Art
Random access memory (RAM) is a typical component of most computer systems. Increasingly, RAM memory is being used as buffer memory in such systems due to the fast operational characteristics of RAM devices. With the increasing speeds of modern computer systems, it is important that RAM devices continue to increase their operational speed. One of the more typical ways to achieve this is to shorten the address access time in a RAM. An alternative approach is to have a shorter data reading time in addition to the faster address access time, even immediately after data writing into the RAM. To address the second demand, the potential level of bit line pairs can be equalized for a given period of time after data writing. The equalizing of the potentials of the bit line pairs will be described in more detail, with reference to prior art.
FIG. 1 shows the essential portions of a typical static RAM (SRAM). A memory cell 51 is an ordinary high-resistance load type cell, and includes first and second driver transistors 61 and 62, first and second transfer transistors 63 and 64, and first and second load resistors R1 and R2. The transistors 61 to 64 each are an N channel MOS transistor. The first transfer transistor 63, connected between a bit line BL and the drain of the first driver transistor 61, has a gate connected to a word line WL. The second transfer transistor 64, connected between the bit line /BL and the drain of the second driver transistor 62, has a gate connected to the word line WL. The first driver transistor 61 has a drain connected via the first load resistor R1 to a power line of a high potential V.sub.CC, a source connected to a power line of a low potential V.sub.SS, and a gate connected to the drain of the second driver transistor 62. The second driver transistor 62 has a drain connected via the second load resistor R2 to the power line of the high potential V.sub.CC, a source connected to the power line of the low potential V.sub.SS, and a gate connected to the drain of the first driver transistor 61.
An equalizer 52 includes three PMOS transistors 65, 66 and 67. The PMOS transistor 65 is connected between the bit lines BL and /BL. The PMOS transistor 66 is connected between the bit line BL and the power line of the high potential V.sub.CC. The PMOS transistor 67 is connected between the bit line /BL and the power line of the high potential V.sub.CC. The individual PMOS transistors 65-67 have gates which receive an equalizer pulse EQ from an external device (not shown). When the equalizer pulse EQ of a L level is input to the gates of the PMOS transistors 65-67, those PMOS transistors 65-67 are turned on. When the PMOS transistor 65 turns on, the pair of bit lines BL and /BL are electrically connected. When the PMOS transistors 66 and 67 turn on, the pair of bit lines BL and /BL and the power line of the high potential V.sub.CC are electrically connected. As a result, the bit lines BL and /BL are pulled up to the high potential V.sub.CC side.
A conventional differential bipolar sense amplifier is incorporated as the sense amplifier 53. The sense amplifier 53 includes first and second emitter followers and a differential amplifier, which will be discussed below.
The first emitter follower has first and second NPN transistors Q1 and Q2, first and second diodes D1 and D2 and first and second NMOS transistors 72 and 74. The first NPN transistor Q1 has a base connected to the bit line BL, a collector connected to the power line of the high potential V.sub.CC and an emitter connected to the power line of the low potential V.sub.SS via the first diode D1 and the first NMOS transistor 72. The second NPN transistor Q2 has a base connected to the bit line /BL, a collector connected to the power line of the high potential V.sub.CC and an emitter connected to the power line of the low potential V.sub.SS, via the second diode D2 and the second NMOS transistor 74.
The differential amplifier in the sense amplifier 53 has two NPN transistors Q3 and Q4, two PMOS transistors 70 and 71 and an NMOS transistor 73. The emitters of both NPN transistors Q3 and Q4 are connected together, and are connected via the NMOS transistor 73 to the power line of the low potential V.sub.SS. The NPN transistor Q3 has a base connected to the cathode of the diode D1, and a collector connected via the PMOS transistor 70 to the power line of the high potential V.sub.CC. The NPN transistor Q4 has a base connected to the cathode of the diode D2, and a collector connected via the PMOS transistor 71 to the power line of the high potential V.sub.CC.
The PMOS transistors 70 and 71 have their gates connected to a reference power supply V.sub.REF, and serve as load resistors of the differential amplifier. The NMOS transistors 72 to 74 also have their gates connected to the reference power supply V.sub.REF, and serve as load resistors of the first emitter follower and the differential amplifier.
The second emitter follower in the sense amplifier 53 has a third and fourth NPN transistors 68 and 69 and a bias power supply. The third NPN transistor 68 has a base connected to the collector of the NPN transistor Q3, a collector connected to the power line of the high potential V.sub.CC and an emitter connected to the power line of the low potential V.sub.SS via the bias power supply. The fourth NPN transistor 69 has a base connected to the collector of the NPN transistor Q4, a collector connected to the power line of the high potential V.sub.CC and an emitter connected to the power line of the low potential V.sub.SS, via the bias power supply. Voltages generated on the bit lines BL and /BL are differentially amplified respectively by the NPN transistors Q3 and Q4, and the amplified voltages are output as output data to a main sense amplifier portion (hereinafter called "MSA") 55 as shown in FIG. 2, through nodes A and B provided between the emitters of the third and fourth NPN transistors 68 and 69 and the bias power supply.
A bit driver 54 shown in FIG. 1 includes two NMOS transistors 77 and 78, and four PMOS transistors 75, 76, 79 and 80. The transistors 75 and 76 are controlled based on a select signal YC from a Y decoder (i.e., column decoder, not shown). The transistors 77 to 80 are controlled based on another select signal YCW. When one of the bit line pairs is selected, the low level select signal YC turns on the associated transistors 75 and 76. When the bit line pair is not selected, a high level select signal turns off the associated transistors 75 and 76. Another select signal YCW is set at a H level during data writing mode, and has an L level during data reading mode and during non-selection of the bit line pair. Accordingly, the pair of bit lines BL and /BL is connected with the sense amplifier 53 during the data writing and reading modes. In the data writing mode, input data Din, /Din, transferred onto the bit lines BL and /BL from a write amplifier (not shown) is written into the associated memory cell 51.
FIG. 2 shows the circuit constitution of the MSA 55 and an output buffer portion 56 in the SRAM. The MSA 55 includes a differential amplifier and an emitter follower which will be discussed below. The MSA's differential amplifier comprises two NPN transistors Q5 and Q6 and two resistors R3 and R4. The emitters of both NPN transistors Q5 and Q6 are connected together to the power line of the low potential V.sub.SS via the bias power supply. The NPN transistor Q5 has a base connected to the node A in the sense amplifier 53 and a collector connected via the resistor R3 to the power line of the high potential V.sub.CC. The NPN transistor Q6 has a base connected to the node B in the sense amplifier 53 and a collector connected via the resistor R4 to the power line of the high potential V.sub.CC. Accordingly, the output of the sense amplifier 53 is differentially amplified by both NPN transistors Q5 and Q6.
The emitter follower of the MSA 55 has first and second NPN transistors 81 and 82 and a bias power supply. The first NPN transistor 81 has a base connected to the collector of the NPN transistor Q5, a collector connected to the power line of the high potential V.sub.CC and an emitter connected via the bias power supply to the power line of the low potential V.sub.SS. The second NPN transistor 82 has a base connected to the collector of the NPN transistor Q6, a collector connected to the power line of the high potential V.sub.CC and an emitter connected via the bias power supply to the power line of the low potential V.sub.SS. Signals differentially amplified respectively by the NPN transistors Q5 and Q6 are output to the output buffer portion 56 via the first and second NPN transistors 81 and 82.
The output buffer portion 56 includes a differential amplifier and an emitter follower which will be discussed below. The differential amplifier comprises three NPN transistors 83, 84 and 23, two resistors R5 and R6, a diode D3 and a bias power supply. The emitters of the individual transistors 83, 84 and 23 are connected together to the power line of the low potential V.sub.SS via the bias power supply. The NPN transistor 83 has a base connected to the emitter of the first NPN transistor 81 and a collector connected via the resistor R5 to the power line of the high potential V.sub.CC. The NPN transistor 84 has a base connected to the emitter of the second NPN transistor 82 and a collector connected via the resistor R6 to the power line of the high potential V.sub.CC. The diode D3 is provided between both NPN transistors 83 and 84. The differential output of the MSA 55 is differentially amplified by both NPN transistors 83 and 84.
The NPN transistor 23 has a collector connected to the collector of the transistor 84 and an emitter connected to the emitter of the transistor 84. The base of the transistor 23 receives a signal SG1 obtained by a logical combination of a write enable signal /WE, a chip select signal /CS and an output enable signal /OE. The logical combined signal SG1 turns on the transistor 23 in order to satisfy the specifications that the output data Dout should maintain an L level at the time of data writing (i.e., when the write enable signal /WE has an L level).
The emitter follower of the output buffer portion 56 is composed of an NPN transistor 85, which has a base connected to the collector of the NPN transistor 84, a collector connected to the power line of the high potential V.sub.CC and an emitter connected to an output terminal 90. A signal differentially amplified by both NPN transistors 83 and 84 is output as output data Dout of the SRAM via the NPN transistor 85 and output terminal 90. When the base of the transistor 23 receives the signal SG1, resulting from the logical combination of the write enable signal /WE, chip select signal /CS and output enable signal /OE at the time of data writing, the NPN transistor 85 is turned off, causing the output data Dout to have an L level.
FIG. 3 shows a time chart which illustrates the levels of an address signal Add, and the write enable signal /WE during the period when, according to the conventional art, data is written to the SRAM. A setup time t.sub.SA is the time from the switching of the address signal, Add, to the falling of the write enable signal /WE to the L level. A holdup time t.sub.HA is the time from the rising of the write enable signal /WE to the H level to the next switching of the address signal Add. An address access time t.sub.AA is the time from the switching of the address signal Add to the point at which the output data Dout corresponding to that selected address is output. A write recovery time t.sub.WR is the time necessary to read data immediately after the data writing. That is, the write recovery time t.sub.WR is the time from the rising of the write enable signal /WE to the point at which the output data Dout, held at the L level for a specific period of time, is established as an output relating to specific write data.
In the conventional SRAM, in reading mode immediately after data writing, the potential levels of the bit lines BL and/BL are equalized for a given period of time after data is written. This equalization process quickens the recovery of the bit lines BL and /BL after data writing. Since the bit lines BL and /BL are equalized, the level difference between both bit lines BL and /BL produced in write mode disappears, and both bit lines BL and/BL have the same potential. This permits the next reading operation to be executed at a high speed.
When the level difference between both bit lines BL and /BL becomes zero, the level of the output signal of the sense amplifier 53 (i.e., the potential levels at the nodes A and B) changes to an intermediate level between that of a high and low level. Consequently, the level of the input signal to the MSA 55 becomes an intermediate level so that the output data Dout temporarily becomes an intermediate level. This phenomenon will be described based on the time chart given in FIG. 4.
Suppose that the write enable signal /WE falls to the L level and the potential at the bit line BL becomes higher than that of the bit line /BL, in accordance with the input data Din, /Din to be written in the memory cell 51. Since an H-level voltage is applied to the base of the transistor Q1 via the bit line BL, the base of the transistor Q3 becomes an H level. Since an L-level voltage is applied to the base of the transistor Q2 via the bit line /BL, the base of the transistor Q4 falls low. During the L-level duration of the write enable signal /WE, the transistor 23 is in an ON state, so that the output data Dout is kept at the L level regardless of the respective status of the bit lines BL and /BL.
Writing of the input data Din, /Din to the memory cell 51 is completed when the write enable signal /WE rises to an H level. The transistor 23 is turned off in synchronism with the completion of that writing, and the transistor 85 tries to output the written data as output data Dout. When writing operation is completed, the equalizer pulse EQ having an L level is input to the equalizer 52 from the external device (not shown). Then, the equalizer 52 short-circuits both bit lines BL and /BL at a potential close to the high potential V.sub.CC to set the potentials of both bit lines BL and /BL equal to each other. As a result, the currents flowing through both transistors Q3 and Q4 in the sense amplifier 53 become equal to each other, and the potentials at the nodes A and B become equal to each other. This sets the base potentials of the transistors Q5 and Q6 of the MSA 55 equal to each other. Therefore, the output data Dout read immediately after data writing temporarily settles at an intermediate potential level, producing a glitch or anomaly in the data reading operation, as shown in FIG. 4.
In order to accelerate the speed of reading data immediately after data writing in the SRAM, it is common to shorten both the address access time t.sub.AA and the write recovery time t.sub.WR. When a glitch occurs in the output data Dout read out immediately after writing, the write recovery time t.sub.WR increases accordingly. As shown in FIG. 4, the write recovery time t.sub.WR2 for the case where a glitch occurs is longer than the write recovery time t.sub.WR1 for the case where no glitch occurs.
Suppose that the switching of the address Add is carried out with a glitch produced, and that H-level output data Dout is read out. Since this output data Dout should rise to the H level from the glitch-based intermediate level, the time for outputting the H-level output data Dout is delayed accordingly. This not only affects the address access time t.sub.AA, but consequently, increases the time for reading data immediately after data writing operations.